Embedded Systems
Design and develop embedded systems with microcontrollers, real-time programming, and hardware interfaces.
Hardware & Embedded
VLSI
Very Large Scale Integration - digital circuit design, CMOS technology, and chip design principles.
All topics in Hardware & Embedded
30‑day curriculum
Day 1 — Introduction to VLSI
Applications, ASIC vs FPGA, Career Paths
Day 2 — Digital Logic Basics
Boolean Algebra, Logic Gates, Truth Tables
Day 3 — Embedded/IoT Foundations I
Adders, Multiplexers, Encoders, Decoders
Day 4 — Sequential Circuits
Flip-Flops, Counters, Registers
Day 5 — Number Systems & Arithmetic
Binary, Gray, ALU basics
Day 6 — VLSI Design Flow
Specification → RTL → Synthesis → Layout → Testing
Day 7 — Mini Project
Design 4-bit Adder & Subtractor (simulation)
Day 8 — Introduction to Verilog
Data types, Operators, Modules
Day 9 — Verilog for Combinational
MUX, DEMUX, Encoder, Decoder
Day 10 — Verilog for Sequential
D Flip-Flop, Counter
Day 11 — Blocking vs Non-Blocking
Blocking vs Non-Blocking Assignments, Always Blocks
Day 12 — Writing Testbenches
Writing Testbenches in Verilog
Day 13 — Simulation Tools
ModelSim, Xilinx Vivado
Day 14 — Mini Project
Design & Simulate 4-bit Counter in Verilog
Day 15 — FPGA Basics
Xilinx/Altera boards, LUTs, CLBs, I/O Blocks
Day 16 — RTL to Gate-Level Synthesis
RTL to Gate-Level Synthesis, Timing Constraints
Day 17 — Memory Elements in Verilog
SRAM, ROM implementation
Day 18 — FSM Design
Finite State Machine Design (Moore, Mealy machines)
Day 19 — Clock Dividers & Counters
Clock Dividers & Counters on FPGA
Day 20 — FPGA Lab Setup
Vivado/Quartus Project Flow
Day 21 — Mini Project
Traffic Light Controller on FPGA
Day 22 — ASIC vs FPGA
ASIC vs FPGA – Where each is used
Day 23 — CMOS Basics
Inverter, NAND/NOR transistor-level design
Day 24 — Standard Cell Libraries
Standard Cell Libraries & Netlists
Day 25 — Static Timing Analysis
Static Timing Analysis (STA) basics
Day 26 — Low-Power VLSI Design
Low-Power VLSI Design Techniques
Day 27 — Physical Design Basics
Floorplanning, Placement, Routing
Day 28 — DFT
Design for Testability, Scan Chains
Day 29 — Final Project Development
Choose one: ALU Design in Verilog / UART Transmitter/Receiver in Verilog / FIFO Memory Design / Digital Clock on FPGA
Day 30 — Final Project Presentation
Final Project Presentation + GitHub Upload + Internship Wrap-Up